This invention relates to a charge transfer device and more particularly, to the structure for applying clock pulses (transfer control signals) to the charge transfer gates.
A conventional charge transfer device includes a large number of charge transfer gate elements arranged in series and is so constructed that the transfer gate elements sequentially transfer a charge in response to a plurality of clock signals having different phases. The charge transfer process of a device of this kind is described in detail on pages 8 to 14, W. S. Boyle and G. E. Smith in "The Bell System Technical Journal", April, 1970.
A conventional charge transfer gate device is constructed in such a manner that one of the charge transfer clock pulses is applied in common to a plurality of transfer gate elements which are not adjacent to each other. In the actual structure, a single signal line for applying a one-phase clock pulse is wired on a chip so as to be in multiple contact with the plurality of transfer gate elements. Accordingly, a distortion of the clock pulse occurs due to the wiring capacitance of this clock signal line, the capacitances of the transfer gate elements and a resistor which is provided to prevent the electrostatic breakdown of the transfer gate elements. This distortion adversely affects charge detection and charge transfer speed. That is, the charge detection is executed, before all of transferred charge is supplied to the charge detection element because of the distortion of the clock pulse applied to the final transfer gate. As a result, correct charge detection can not be obtained.
On the other hand, this shortcoming can be avoided by detection over a long period of time. However, the long detection period results in a decrease in device operating speed.
In actual operation, a distorted clock pulse applied to the transfer gate element of the final stage shows the change of the potential well under the gate. As a result, the transfer of charge to the detection element through the output gate (which is normally fixed at a predetermined potential) is delayed and hence, the charge detection element must be controlled to allow for this delay. This makes it impossible to obtain high speed operation of the device. Furthermore, the charge transferred via the transfer gate element of the final stage must be held for a predetermined period of time in the detection element for accurate detection of the transferred charge. To satisfy this object, the detection element is constructed so that a predetermined holding time can be set. The holding time is a period from the time when all of the transferred charge is stored in the detection element to the time when a reset pulse is applied to the detection element. However, this holding time of the prior art device must be set to a longer period in consideration of the delay, because the transfer of the charge from the transfer gate element of the final stage is delayed by the distortion of the clock pulse. If the clock pulse is a 5 MHz signal, for example, a reset signal with a maximum value of only approximately 5 MHz can be applied to the charge detection element of a conventional charge transfer device. In other words, since the operating speed of the device is determined by the control speed of the charge detection element, high speed operation cannot be obtained from the conventional device for the reasons described above.